;--------------------------------------------------------
; File Created by SDCC : free open source ANSI-C Compiler
; Version 2.9.0 #5416 (Feb  3 2010) (UNIX)
; This file was generated Thu May 12 01:17:15 2011
;--------------------------------------------------------
; PIC16 port for the Microchip 16-bit core micros
;--------------------------------------------------------

	.ident "SDCC version 2.9.0 #5416 [pic16 port]"
	.file	"ir_test.c"
	list	p=18f2550
	__config 0x300000, 0xc4
	__config 0x300001, 0x3c
	__config 0x300002, 0xf7
	__config 0x300003, 0xfe
	__config 0x300005, 0xf8
	__config 0x300006, 0x9b
	__config 0x300008, 0xff
	__config 0x300009, 0xff
	__config 0x30000a, 0xff
	__config 0x30000b, 0xff
	__config 0x30000c, 0xff
	__config 0x30000d, 0xff

	radix dec

;--------------------------------------------------------
; public variables in this module
;--------------------------------------------------------
	global _i_long
	global _tx_data
	global _ad1
	global _ad0
	global _timer_2_copy
	global _rs232_transmit
	global _rs232_receive
	global _send_space
	global _send_mark
	global _sleep_ms
	global _debug_led
	global _debug
	global _to_binary_str
	global _timer_2
	global _rx_data
	global _tx_bit_counter
	global _i
	global _serial_packet
	global _serial_packet_bit_counter
	global _main

;--------------------------------------------------------
; extern variables in this module
;--------------------------------------------------------
	extern __gptrput1
	extern __gptrget1
	extern _SPPDATAbits
	extern _SPPCFGbits
	extern _SPPEPSbits
	extern _SPPCONbits
	extern _UFRMLbits
	extern _UFRMHbits
	extern _UIRbits
	extern _UIEbits
	extern _UEIRbits
	extern _UEIEbits
	extern _USTATbits
	extern _UCONbits
	extern _UADDRbits
	extern _UCFGbits
	extern _UEP0bits
	extern _UEP1bits
	extern _UEP2bits
	extern _UEP3bits
	extern _UEP4bits
	extern _UEP5bits
	extern _UEP6bits
	extern _UEP7bits
	extern _UEP8bits
	extern _UEP9bits
	extern _UEP10bits
	extern _UEP11bits
	extern _UEP12bits
	extern _UEP13bits
	extern _UEP14bits
	extern _UEP15bits
	extern _PORTAbits
	extern _PORTBbits
	extern _PORTCbits
	extern _PORTDbits
	extern _PORTEbits
	extern _LATAbits
	extern _LATBbits
	extern _LATCbits
	extern _LATDbits
	extern _LATEbits
	extern _TRISAbits
	extern _TRISBbits
	extern _TRISCbits
	extern _TRISDbits
	extern _TRISEbits
	extern _OSCTUNEbits
	extern _PIE1bits
	extern _PIR1bits
	extern _IPR1bits
	extern _PIE2bits
	extern _PIR2bits
	extern _IPR2bits
	extern _EECON1bits
	extern _RCSTAbits
	extern _TXSTAbits
	extern _T3CONbits
	extern _CMCONbits
	extern _CVRCONbits
	extern _ECCP1ASbits
	extern _ECCP1DELbits
	extern _BAUDCONbits
	extern _CCP2CONbits
	extern _CCP1CONbits
	extern _ADCON2bits
	extern _ADCON1bits
	extern _ADCON0bits
	extern _SSPCON2bits
	extern _SSPCON1bits
	extern _SSPSTATbits
	extern _T2CONbits
	extern _T1CONbits
	extern _RCONbits
	extern _WDTCONbits
	extern _HLVDCONbits
	extern _OSCCONbits
	extern _T0CONbits
	extern _STATUSbits
	extern _FSR2Hbits
	extern _BSRbits
	extern _FSR1Hbits
	extern _FSR0Hbits
	extern _INTCON3bits
	extern _INTCON2bits
	extern _INTCONbits
	extern _TBLPTRUbits
	extern _PCLATHbits
	extern _PCLATUbits
	extern _STKPTRbits
	extern _TOSUbits
	extern _stdin
	extern _stdout
	extern _SPPDATA
	extern _SPPCFG
	extern _SPPEPS
	extern _SPPCON
	extern _UFRML
	extern _UFRMH
	extern _UIR
	extern _UIE
	extern _UEIR
	extern _UEIE
	extern _USTAT
	extern _UCON
	extern _UADDR
	extern _UCFG
	extern _UEP0
	extern _UEP1
	extern _UEP2
	extern _UEP3
	extern _UEP4
	extern _UEP5
	extern _UEP6
	extern _UEP7
	extern _UEP8
	extern _UEP9
	extern _UEP10
	extern _UEP11
	extern _UEP12
	extern _UEP13
	extern _UEP14
	extern _UEP15
	extern _PORTA
	extern _PORTB
	extern _PORTC
	extern _PORTD
	extern _PORTE
	extern _LATA
	extern _LATB
	extern _LATC
	extern _LATD
	extern _LATE
	extern _TRISA
	extern _TRISB
	extern _TRISC
	extern _TRISD
	extern _TRISE
	extern _OSCTUNE
	extern _PIE1
	extern _PIR1
	extern _IPR1
	extern _PIE2
	extern _PIR2
	extern _IPR2
	extern _EECON1
	extern _EECON2
	extern _EEDATA
	extern _EEADR
	extern _RCSTA
	extern _TXSTA
	extern _TXREG
	extern _RCREG
	extern _SPBRG
	extern _SPBRGH
	extern _T3CON
	extern _TMR3L
	extern _TMR3H
	extern _CMCON
	extern _CVRCON
	extern _ECCP1AS
	extern _ECCP1DEL
	extern _BAUDCON
	extern _CCP2CON
	extern _CCPR2L
	extern _CCPR2H
	extern _CCP1CON
	extern _CCPR1L
	extern _CCPR1H
	extern _ADCON2
	extern _ADCON1
	extern _ADCON0
	extern _ADRESL
	extern _ADRESH
	extern _SSPCON2
	extern _SSPCON1
	extern _SSPSTAT
	extern _SSPADD
	extern _SSPBUF
	extern _T2CON
	extern _PR2
	extern _TMR2
	extern _T1CON
	extern _TMR1L
	extern _TMR1H
	extern _RCON
	extern _WDTCON
	extern _HLVDCON
	extern _OSCCON
	extern _T0CON
	extern _TMR0L
	extern _TMR0H
	extern _STATUS
	extern _FSR2L
	extern _FSR2H
	extern _PLUSW2
	extern _PREINC2
	extern _POSTDEC2
	extern _POSTINC2
	extern _INDF2
	extern _BSR
	extern _FSR1L
	extern _FSR1H
	extern _PLUSW1
	extern _PREINC1
	extern _POSTDEC1
	extern _POSTINC1
	extern _INDF1
	extern _WREG
	extern _FSR0L
	extern _FSR0H
	extern _PLUSW0
	extern _PREINC0
	extern _POSTDEC0
	extern _POSTINC0
	extern _INDF0
	extern _INTCON3
	extern _INTCON2
	extern _INTCON
	extern _PRODL
	extern _PRODH
	extern _TABLAT
	extern _TBLPTRL
	extern _TBLPTRH
	extern _TBLPTRU
	extern _PCL
	extern _PCLATH
	extern _PCLATU
	extern _STKPTR
	extern _TOSL
	extern _TOSH
	extern _TOSU
	extern _adc_open
	extern _adc_conv
	extern _adc_busy
	extern _adc_read
	extern _adc_setchannel
	extern _sprintf
	extern _usart_open
	extern _usart_close
	extern _usart_drdy
	extern _usart_getc
	extern _lcd_init
	extern _lcd_clear
	extern _lcd_ddram
	extern _send_data
	extern _init_protocol
	extern _get_protocol_data
	extern _add_to_protocol_decoder
	extern _add_packet_to_protocol_encoder
	extern _encode_frame
	extern __mullong
;--------------------------------------------------------
;	Equates to used internal registers
;--------------------------------------------------------
STATUS	equ	0xfd8
PCLATH	equ	0xffa
PCLATU	equ	0xffb
WREG	equ	0xfe8
BSR	equ	0xfe0
FSR0L	equ	0xfe9
FSR0H	equ	0xfea
FSR1L	equ	0xfe1
FSR2L	equ	0xfd9
INDF0	equ	0xfef
POSTDEC1	equ	0xfe5
PREINC1	equ	0xfe4
PLUSW2	equ	0xfdb
PRODL	equ	0xff3
PRODH	equ	0xff4


; Internal registers
.registers	udata_ovr	0x0000
r0x00	res	1
r0x01	res	1
r0x02	res	1
r0x03	res	1
r0x04	res	1
r0x05	res	1
r0x06	res	1
r0x07	res	1
r0x08	res	1
r0x09	res	1
r0x0a	res	1
r0x0b	res	1
r0x0c	res	1
r0x0d	res	1
r0x0e	res	1
r0x0f	res	1
r0x10	res	1
r0x11	res	1
r0x12	res	1

udata_ir_test_0	udata
_timer_2_copy	res	4

udata_ir_test_1	udata
_ad0	res	1

udata_ir_test_2	udata
_ad1	res	1

udata_ir_test_3	udata
_tx_data	res	1

udata_ir_test_4	udata
_i_long	res	4

udata_ir_test_5	udata
_timer_2	res	4

udata_ir_test_6	udata
_i	res	1

udata_ir_test_7	udata
_main_packets_1_1	res	19

udata_ir_test_8	udata
_main_frame_1_1	res	47

udata_ir_test_9	udata
_main_packet_1_1	res	9

udata_ir_test_10	udata
_rx_data	res	1

udata_ir_test_11	udata
_main_rx_packets_1_1	res	19

udata_ir_test_12	udata
_main_lcd_buf_1_1	res	16

udata_ir_test_13	udata
_serial_packet	res	2

udata_ir_test_14	udata
_serial_packet_bit_counter	res	1

udata_ir_test_15	udata
_tx_bit_counter	res	1

;--------------------------------------------------------
; interrupt vector 
;--------------------------------------------------------

;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
; ; Starting pCode block for absolute section
; ;-----------------------------------------
S_ir_test_ivec_0x1_phase_control	code	0X000008
ivec_0x1_phase_control:
	GOTO	_phase_control

; ; Starting pCode block for absolute section
; ;-----------------------------------------
S_ir_test_ivec_0x2_timer_control	code	0X000018
ivec_0x2_timer_control:
	GOTO	_timer_control

; I code from now on!
; ; Starting pCode block
S_ir_test__main	code
_main:
	.line	42; ir_test.c	OSCCONbits.SCS = 0x0;		// System Clock Select bits = External oscillator
	MOVF	_OSCCONbits, W
	ANDLW	0xfc
	MOVWF	_OSCCONbits
	.line	43; ir_test.c	OSCCONbits.IRCF = 0x7;		// Internal Oscillator Frequency Select bits 8 MHz (INTOSC drives clock directly)
	MOVF	_OSCCONbits, W
	ANDLW	0x8f
	IORLW	0x70
	MOVWF	_OSCCONbits
	.line	46; ir_test.c	TRISAbits.TRISA0 = 1;	// ad 0
	BSF	_TRISAbits, 0
	.line	47; ir_test.c	TRISAbits.TRISA1 = 1;	// ad 1
	BSF	_TRISAbits, 1
	.line	49; ir_test.c	TRISBbits.TRISB5 = 0;	// LED as output
	BCF	_TRISBbits, 5
	.line	50; ir_test.c	TRISCbits.TRISC6 = 0;	// TX_PIN as output
	BCF	_TRISCbits, 6
	.line	51; ir_test.c	TRISCbits.TRISC7 = 1;	// RX_PIN as input
	BSF	_TRISCbits, 7
	BANKSEL	_timer_2
	.line	53; ir_test.c	timer_2 = 0;
	CLRF	_timer_2, B
	BANKSEL	(_timer_2 + 1)
	CLRF	(_timer_2 + 1), B
	BANKSEL	(_timer_2 + 2)
	CLRF	(_timer_2 + 2), B
	BANKSEL	(_timer_2 + 3)
	CLRF	(_timer_2 + 3), B
	.line	57; ir_test.c	adc_open(2, ADC_FOSC_64, ADC_CFG_2A, ADC_FRM_RJUST | ADC_INT_OFF);
	MOVLW	0x80
	MOVWF	POSTDEC1
	MOVLW	0x0d
	MOVWF	POSTDEC1
	MOVLW	0x06
	MOVWF	POSTDEC1
	MOVLW	0x02
	MOVWF	POSTDEC1
	CALL	_adc_open
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	61; ir_test.c	RCONbits.IPEN = 1;
	BSF	_RCONbits, 7
	.line	64; ir_test.c	T0CONbits.TMR0ON = 0;
	BCF	_T0CONbits, 7
	.line	65; ir_test.c	T0CONbits.T08BIT = 0;	// use timer0 16-bit counter
	BCF	_T0CONbits, 6
	.line	66; ir_test.c	T0CONbits.T0CS = 0;		// internal clock source
	BCF	_T0CONbits, 5
	.line	67; ir_test.c	T0CONbits.PSA = 1;		// disable timer0 prescaler
	BSF	_T0CONbits, 3
	.line	68; ir_test.c	INTCON2bits.TMR0IP = 1;	// high priority
	BSF	_INTCON2bits, 2
	.line	71; ir_test.c	T1CONbits.TMR1ON = 0;
	BCF	_T1CONbits, 0
	.line	72; ir_test.c	T1CONbits.RD16 = 1;
	BSF	_T1CONbits, 7
	.line	73; ir_test.c	T1CONbits.TMR1CS = 0;	// internal clock source
	BCF	_T1CONbits, 1
	.line	74; ir_test.c	T1CONbits.T1OSCEN = 0;	// dont put t1 on pin
	BCF	_T1CONbits, 3
	.line	75; ir_test.c	T1CONbits.T1CKPS0 = 1;
	BSF	_T1CONbits, 4
	.line	76; ir_test.c	T1CONbits.T1CKPS1 = 1;
	BSF	_T1CONbits, 5
	.line	77; ir_test.c	IPR1bits.TMR1IP = 0;		// low priority
	BCF	_IPR1bits, 0
	.line	80; ir_test.c	T2CONbits.T2CKPS0 = 1;
	BSF	_T2CONbits, 0
	.line	81; ir_test.c	T2CONbits.T2CKPS1 = 0;
	BCF	_T2CONbits, 1
	.line	82; ir_test.c	T2CONbits.TOUTPS0 = 1;
	BSF	_T2CONbits, 3
	.line	83; ir_test.c	T2CONbits.TOUTPS1 = 0;
	BCF	_T2CONbits, 4
	.line	84; ir_test.c	T2CONbits.TOUTPS2 = 0;
	BCF	_T2CONbits, 5
	.line	85; ir_test.c	T2CONbits.TOUTPS3 = 1;
	BSF	_T2CONbits, 6
	.line	86; ir_test.c	IPR1bits.TMR2IP = 0;		// low priority
	BCF	_IPR1bits, 1
	.line	87; ir_test.c	PIR1bits.TMR2IF = 1;
	BSF	_PIR1bits, 1
	.line	88; ir_test.c	T2CONbits.TMR2ON = 1;
	BSF	_T2CONbits, 2
	.line	89; ir_test.c	PIE1bits.TMR2IE = 1;
	BSF	_PIE1bits, 1
	.line	92; ir_test.c	T3CONbits.RD16 = 1;
	BSF	_T3CONbits, 7
	.line	93; ir_test.c	T3CONbits.TMR3CS = 0;	// internal clock source
	BCF	_T3CONbits, 1
	.line	94; ir_test.c	T3CONbits.T3CKPS0 = 1;
	BSF	_T3CONbits, 4
	.line	95; ir_test.c	T3CONbits.T3CKPS0 = 1;
	BSF	_T3CONbits, 4
	.line	96; ir_test.c	IPR2bits.TMR3IP = 0;		// low priority
	BCF	_IPR2bits, 1
	.line	97; ir_test.c	T3CONbits.TMR3ON = 1;
	BSF	_T3CONbits, 0
	.line	98; ir_test.c	PIE2bits.TMR3IE = 1;
	BSF	_PIE2bits, 1
	.line	99; ir_test.c	PIR2bits.TMR3IF = 1;
	BSF	_PIR2bits, 1
	.line	101; ir_test.c	INTCONbits.PEIE = 1;
	BSF	_INTCONbits, 6
	.line	102; ir_test.c	INTCONbits.GIE = 1;
	BSF	_INTCONbits, 7
	.line	104; ir_test.c	TRISAbits.TRISA2 = 1;
	BSF	_TRISAbits, 2
	.line	113; ir_test.c	if (PORTAbits.RA2) {
	BTFSS	_PORTAbits, 2
	BRA	_00117_DS_
	BANKSEL	_tx_data
	.line	116; ir_test.c	tx_data = 0;
	CLRF	_tx_data, B
_00106_DS_:
	.line	118; ir_test.c	init_protocol(&packets, frame);
	MOVLW	HIGH(_main_packets_1_1)
	MOVWF	r0x01
	MOVLW	LOW(_main_packets_1_1)
	MOVWF	r0x00
	MOVLW	0x80
	MOVWF	r0x02
	MOVLW	HIGH(_main_frame_1_1)
	MOVWF	r0x04
	MOVLW	LOW(_main_frame_1_1)
	MOVWF	r0x03
	MOVLW	0x80
	MOVWF	r0x05
	MOVF	r0x05, W
	MOVWF	POSTDEC1
	MOVF	r0x04, W
	MOVWF	POSTDEC1
	MOVF	r0x03, W
	MOVWF	POSTDEC1
	MOVF	r0x02, W
	MOVWF	POSTDEC1
	MOVF	r0x01, W
	MOVWF	POSTDEC1
	MOVF	r0x00, W
	MOVWF	POSTDEC1
	CALL	_init_protocol
	MOVLW	0x06
	ADDWF	FSR1L, F
	.line	119; ir_test.c	timer_2_copy = timer_2;
	MOVFF	_timer_2, _timer_2_copy
	MOVFF	(_timer_2 + 1), (_timer_2_copy + 1)
	MOVFF	(_timer_2 + 2), (_timer_2_copy + 2)
	MOVFF	(_timer_2 + 3), (_timer_2_copy + 3)
	.line	121; ir_test.c	packet.cmd = cmd;
	MOVLW	0x01
	BANKSEL	_main_packet_1_1
	MOVWF	_main_packet_1_1, B
	BANKSEL	(_main_packet_1_1 + 1)
	.line	122; ir_test.c	packet.params[0] = 0; //timer_2_copy;
	CLRF	(_main_packet_1_1 + 1), B
	BANKSEL	(_main_packet_1_1 + 2)
	.line	123; ir_test.c	packet.params[1] = 0; //timer_2_copy >> 8;
	CLRF	(_main_packet_1_1 + 2), B
	BANKSEL	(_main_packet_1_1 + 3)
	.line	124; ir_test.c	packet.params[2] = 0; //timer_2_copy >> 16;
	CLRF	(_main_packet_1_1 + 3), B
	BANKSEL	(_main_packet_1_1 + 4)
	.line	125; ir_test.c	packet.params[3] = 0; //timer_2_copy >> 24;
	CLRF	(_main_packet_1_1 + 4), B
	BANKSEL	(_main_packet_1_1 + 5)
	.line	126; ir_test.c	packet.params[4] = 0;
	CLRF	(_main_packet_1_1 + 5), B
	BANKSEL	(_main_packet_1_1 + 6)
	.line	127; ir_test.c	packet.params[5] = 0;
	CLRF	(_main_packet_1_1 + 6), B
	BANKSEL	(_main_packet_1_1 + 7)
	.line	128; ir_test.c	packet.params[6] = 0;
	CLRF	(_main_packet_1_1 + 7), B
	BANKSEL	(_main_packet_1_1 + 8)
	.line	129; ir_test.c	packet.params[7] = 0;
	CLRF	(_main_packet_1_1 + 8), B
	.line	130; ir_test.c	add_packet_to_protocol_encoder(&packet);
	MOVLW	HIGH(_main_packet_1_1)
	MOVWF	r0x01
	MOVLW	LOW(_main_packet_1_1)
	MOVWF	r0x00
	MOVLW	0x80
	MOVWF	r0x02
	MOVF	r0x02, W
	MOVWF	POSTDEC1
	MOVF	r0x01, W
	MOVWF	POSTDEC1
	MOVF	r0x00, W
	MOVWF	POSTDEC1
	CALL	_add_packet_to_protocol_encoder
	MOVLW	0x03
	ADDWF	FSR1L, F
	.line	133; ir_test.c	packet.cmd = cmd;
	MOVLW	0x02
	BANKSEL	_main_packet_1_1
	MOVWF	_main_packet_1_1, B
	BANKSEL	(_main_packet_1_1 + 1)
	.line	134; ir_test.c	packet.params[0] = 0;
	CLRF	(_main_packet_1_1 + 1), B
	.line	135; ir_test.c	packet.params[1] = 1;
	MOVLW	0x01
	BANKSEL	(_main_packet_1_1 + 2)
	MOVWF	(_main_packet_1_1 + 2), B
	.line	136; ir_test.c	packet.params[2] = 7;
	MOVLW	0x07
	BANKSEL	(_main_packet_1_1 + 3)
	MOVWF	(_main_packet_1_1 + 3), B
	.line	137; ir_test.c	packet.params[3] = 2;
	MOVLW	0x02
	BANKSEL	(_main_packet_1_1 + 4)
	MOVWF	(_main_packet_1_1 + 4), B
	BANKSEL	(_main_packet_1_1 + 5)
	.line	138; ir_test.c	packet.params[4] = 0;
	CLRF	(_main_packet_1_1 + 5), B
	BANKSEL	(_main_packet_1_1 + 6)
	.line	139; ir_test.c	packet.params[5] = 0;
	CLRF	(_main_packet_1_1 + 6), B
	BANKSEL	(_main_packet_1_1 + 7)
	.line	140; ir_test.c	packet.params[6] = 0;
	CLRF	(_main_packet_1_1 + 7), B
	BANKSEL	(_main_packet_1_1 + 8)
	.line	141; ir_test.c	packet.params[7] = 0;
	CLRF	(_main_packet_1_1 + 8), B
	.line	142; ir_test.c	add_packet_to_protocol_encoder(&packet);
	MOVLW	HIGH(_main_packet_1_1)
	MOVWF	r0x01
	MOVLW	LOW(_main_packet_1_1)
	MOVWF	r0x00
	MOVLW	0x80
	MOVWF	r0x02
	MOVF	r0x02, W
	MOVWF	POSTDEC1
	MOVF	r0x01, W
	MOVWF	POSTDEC1
	MOVF	r0x00, W
	MOVWF	POSTDEC1
	CALL	_add_packet_to_protocol_encoder
	MOVLW	0x03
	ADDWF	FSR1L, F
	.line	148; ir_test.c	encode_frame(37, 255);
	MOVLW	0xff
	MOVWF	POSTDEC1
	MOVLW	0x25
	MOVWF	POSTDEC1
	CALL	_encode_frame
	MOVLW	0x02
	ADDWF	FSR1L, F
	BANKSEL	_i
	.line	176; ir_test.c	for (i = 0; i < FRAME_LENGTH; i++) {
	CLRF	_i, B
_00119_DS_:
	MOVLW	0x2f
	BANKSEL	_i
	SUBWF	_i, W, B
	BTFSC	STATUS, 0
	BRA	_00106_DS_
	.line	178; ir_test.c	rs232_transmit(frame[i]);
	MOVLW	LOW(_main_frame_1_1)
	BANKSEL	_i
	ADDWF	_i, W, B
	MOVWF	r0x00
	CLRF	r0x01
	MOVLW	HIGH(_main_frame_1_1)
	ADDWFC	r0x01, F
	MOVFF	r0x00, FSR0L
	MOVFF	r0x01, FSR0H
	MOVFF	INDF0, r0x00
	MOVF	r0x00, W
	MOVWF	POSTDEC1
	CALL	_rs232_transmit
	INCF	FSR1L, F
	BANKSEL	_i
	.line	176; ir_test.c	for (i = 0; i < FRAME_LENGTH; i++) {
	INCF	_i, F, B
	BRA	_00119_DS_
_00117_DS_:
	.line	186; ir_test.c	lcd_init();
	CALL	_lcd_init
_00114_DS_:
	.line	188; ir_test.c	init_protocol(&packets, frame);
	MOVLW	HIGH(_main_packets_1_1)
	MOVWF	r0x01
	MOVLW	LOW(_main_packets_1_1)
	MOVWF	r0x00
	MOVLW	0x80
	MOVWF	r0x02
	MOVLW	HIGH(_main_frame_1_1)
	MOVWF	r0x04
	MOVLW	LOW(_main_frame_1_1)
	MOVWF	r0x03
	MOVLW	0x80
	MOVWF	r0x05
	MOVF	r0x05, W
	MOVWF	POSTDEC1
	MOVF	r0x04, W
	MOVWF	POSTDEC1
	MOVF	r0x03, W
	MOVWF	POSTDEC1
	MOVF	r0x02, W
	MOVWF	POSTDEC1
	MOVF	r0x01, W
	MOVWF	POSTDEC1
	MOVF	r0x00, W
	MOVWF	POSTDEC1
	CALL	_init_protocol
	MOVLW	0x06
	ADDWF	FSR1L, F
_00110_DS_:
	.line	189; ir_test.c	while (rs232_receive(&rx_data, RX_TIMEOUT) > 0) {
	MOVLW	HIGH(_rx_data)
	MOVWF	r0x01
	MOVLW	LOW(_rx_data)
	MOVWF	r0x00
	MOVLW	0x80
	MOVWF	r0x02
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x1f
	MOVWF	POSTDEC1
	MOVLW	0x40
	MOVWF	POSTDEC1
	MOVF	r0x02, W
	MOVWF	POSTDEC1
	MOVF	r0x01, W
	MOVWF	POSTDEC1
	MOVF	r0x00, W
	MOVWF	POSTDEC1
	CALL	_rs232_receive
	MOVWF	r0x00
	MOVLW	0x07
	ADDWF	FSR1L, F
	MOVF	r0x00, W
	BZ	_00114_DS_
	BANKSEL	_rx_data
	.line	190; ir_test.c	add_to_protocol_decoder(rx_data);
	MOVF	_rx_data, W, B
	MOVWF	POSTDEC1
	CALL	_add_to_protocol_decoder
	INCF	FSR1L, F
	.line	191; ir_test.c	if (get_protocol_data(&rx_packets) > 0) {
	MOVLW	HIGH(_main_rx_packets_1_1)
	MOVWF	r0x01
	MOVLW	LOW(_main_rx_packets_1_1)
	MOVWF	r0x00
	MOVLW	0x80
	MOVWF	r0x02
	MOVF	r0x02, W
	MOVWF	POSTDEC1
	MOVF	r0x01, W
	MOVWF	POSTDEC1
	MOVF	r0x00, W
	MOVWF	POSTDEC1
	CALL	_get_protocol_data
	MOVWF	r0x00
	MOVLW	0x03
	ADDWF	FSR1L, F
	MOVF	r0x00, W
	BZ	_00110_DS_
	.line	205; ir_test.c	rx_packets.packet[0].params[4], rx_packets.packet[0].params[5], rx_packets.packet[0].params[6], rx_packets.packet[0].params[7]);
	MOVFF	(_main_rx_packets_1_1 + 8), r0x00
	CLRF	r0x01
	BANKSEL	(_main_rx_packets_1_1 + 8)
	BTFSC	(_main_rx_packets_1_1 + 8), 7
	SETF	r0x01
	MOVFF	(_main_rx_packets_1_1 + 7), r0x02
	CLRF	r0x03
	BANKSEL	(_main_rx_packets_1_1 + 7)
	BTFSC	(_main_rx_packets_1_1 + 7), 7
	SETF	r0x03
	MOVFF	(_main_rx_packets_1_1 + 6), r0x04
	CLRF	r0x05
	BANKSEL	(_main_rx_packets_1_1 + 6)
	BTFSC	(_main_rx_packets_1_1 + 6), 7
	SETF	r0x05
	MOVFF	(_main_rx_packets_1_1 + 5), r0x06
	CLRF	r0x07
	BANKSEL	(_main_rx_packets_1_1 + 5)
	BTFSC	(_main_rx_packets_1_1 + 5), 7
	SETF	r0x07
	.line	204; ir_test.c	rx_packets.packet[0].params[0], rx_packets.packet[0].params[1], rx_packets.packet[0].params[2], rx_packets.packet[0].params[3], 
	MOVFF	(_main_rx_packets_1_1 + 4), r0x08
	CLRF	r0x09
	BANKSEL	(_main_rx_packets_1_1 + 4)
	BTFSC	(_main_rx_packets_1_1 + 4), 7
	SETF	r0x09
	MOVFF	(_main_rx_packets_1_1 + 3), r0x0a
	CLRF	r0x0b
	BANKSEL	(_main_rx_packets_1_1 + 3)
	BTFSC	(_main_rx_packets_1_1 + 3), 7
	SETF	r0x0b
	MOVFF	(_main_rx_packets_1_1 + 2), r0x0c
	CLRF	r0x0d
	BANKSEL	(_main_rx_packets_1_1 + 2)
	BTFSC	(_main_rx_packets_1_1 + 2), 7
	SETF	r0x0d
	MOVFF	(_main_rx_packets_1_1 + 1), r0x0e
	CLRF	r0x0f
	BANKSEL	(_main_rx_packets_1_1 + 1)
	BTFSC	(_main_rx_packets_1_1 + 1), 7
	SETF	r0x0f
	.line	203; ir_test.c	sprintf(lcd_buf, "%02x%02x%02x%02x%02x%02x%02x%02x", 
	MOVLW	HIGH(_main_lcd_buf_1_1)
	MOVWF	r0x11
	MOVLW	LOW(_main_lcd_buf_1_1)
	MOVWF	r0x10
	MOVLW	0x80
	MOVWF	r0x12
	MOVF	r0x01, W
	MOVWF	POSTDEC1
	MOVF	r0x00, W
	MOVWF	POSTDEC1
	MOVF	r0x03, W
	MOVWF	POSTDEC1
	MOVF	r0x02, W
	MOVWF	POSTDEC1
	MOVF	r0x05, W
	MOVWF	POSTDEC1
	MOVF	r0x04, W
	MOVWF	POSTDEC1
	MOVF	r0x07, W
	MOVWF	POSTDEC1
	MOVF	r0x06, W
	MOVWF	POSTDEC1
	MOVF	r0x09, W
	MOVWF	POSTDEC1
	MOVF	r0x08, W
	MOVWF	POSTDEC1
	MOVF	r0x0b, W
	MOVWF	POSTDEC1
	MOVF	r0x0a, W
	MOVWF	POSTDEC1
	MOVF	r0x0d, W
	MOVWF	POSTDEC1
	MOVF	r0x0c, W
	MOVWF	POSTDEC1
	MOVF	r0x0f, W
	MOVWF	POSTDEC1
	MOVF	r0x0e, W
	MOVWF	POSTDEC1
	MOVLW	UPPER(__str_0)
	MOVWF	POSTDEC1
	MOVLW	HIGH(__str_0)
	MOVWF	POSTDEC1
	MOVLW	LOW(__str_0)
	MOVWF	POSTDEC1
	MOVF	r0x12, W
	MOVWF	POSTDEC1
	MOVF	r0x11, W
	MOVWF	POSTDEC1
	MOVF	r0x10, W
	MOVWF	POSTDEC1
	CALL	_sprintf
	MOVLW	0x16
	ADDWF	FSR1L, F
	.line	206; ir_test.c	debug(lcd_buf);
	MOVLW	HIGH(_main_lcd_buf_1_1)
	MOVWF	r0x01
	MOVLW	LOW(_main_lcd_buf_1_1)
	MOVWF	r0x00
	MOVLW	0x80
	MOVWF	r0x02
	MOVF	r0x02, W
	MOVWF	POSTDEC1
	MOVF	r0x01, W
	MOVWF	POSTDEC1
	MOVF	r0x00, W
	MOVWF	POSTDEC1
	CALL	_debug
	MOVLW	0x03
	ADDWF	FSR1L, F
	.line	207; ir_test.c	sleep_ms(1000);
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x03
	MOVWF	POSTDEC1
	MOVLW	0xe8
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	209; ir_test.c	break;
	BRA	_00114_DS_
	RETURN	

; ; Starting pCode block
S_ir_test__to_binary_str	code
_to_binary_str:
	.line	411; ir_test.c	void to_binary_str(unsigned char *buf, unsigned char n) {
	MOVFF	FSR2L, POSTDEC1
	MOVFF	FSR1L, FSR2L
	MOVFF	r0x00, POSTDEC1
	MOVFF	r0x01, POSTDEC1
	MOVFF	r0x02, POSTDEC1
	MOVFF	r0x03, POSTDEC1
	MOVFF	r0x04, POSTDEC1
	MOVFF	r0x05, POSTDEC1
	MOVFF	r0x06, POSTDEC1
	MOVFF	r0x07, POSTDEC1
	MOVFF	r0x08, POSTDEC1
	MOVLW	0x02
	MOVFF	PLUSW2, r0x00
	MOVLW	0x03
	MOVFF	PLUSW2, r0x01
	MOVLW	0x04
	MOVFF	PLUSW2, r0x02
	MOVLW	0x05
	MOVFF	PLUSW2, r0x03
	.line	413; ir_test.c	for (i = 0; i < 8; i++) {
	CLRF	r0x04
_00279_DS_:
	MOVLW	0x08
	SUBWF	r0x04, W
	BTFSC	STATUS, 0
	BRA	_00282_DS_
	.line	414; ir_test.c	if (n & (1 << i)) {
	MOVLW	0x01
	MOVWF	r0x05
	MOVLW	0x00
	MOVWF	r0x06
	MOVF	r0x04, W
	BZ	_00290_DS_
	NEGF	WREG
	BCF	STATUS, 0
_00291_DS_:
	RLCF	r0x05, F
	RLCF	r0x06, F
	ADDLW	0x01
	BNC	_00291_DS_
_00290_DS_:
	MOVFF	r0x03, r0x07
	CLRF	r0x08
	MOVF	r0x07, W
	ANDWF	r0x05, F
	MOVF	r0x08, W
	ANDWF	r0x06, F
	MOVF	r0x05, W
	IORWF	r0x06, W
	BZ	_00277_DS_
	.line	415; ir_test.c	buf[i] = '1';
	MOVF	r0x04, W
	ADDWF	r0x00, W
	MOVWF	r0x05
	CLRF	WREG
	ADDWFC	r0x01, W
	MOVWF	r0x06
	CLRF	WREG
	ADDWFC	r0x02, W
	MOVWF	r0x07
	MOVLW	0x31
	MOVWF	POSTDEC1
	MOVFF	r0x05, FSR0L
	MOVFF	r0x06, PRODL
	MOVF	r0x07, W
	CALL	__gptrput1
	BRA	_00281_DS_
_00277_DS_:
	.line	418; ir_test.c	buf[i] = '0';
	MOVF	r0x04, W
	ADDWF	r0x00, W
	MOVWF	r0x05
	CLRF	WREG
	ADDWFC	r0x01, W
	MOVWF	r0x06
	CLRF	WREG
	ADDWFC	r0x02, W
	MOVWF	r0x07
	MOVLW	0x30
	MOVWF	POSTDEC1
	MOVFF	r0x05, FSR0L
	MOVFF	r0x06, PRODL
	MOVF	r0x07, W
	CALL	__gptrput1
_00281_DS_:
	.line	413; ir_test.c	for (i = 0; i < 8; i++) {
	INCF	r0x04, F
	BRA	_00279_DS_
_00282_DS_:
	.line	421; ir_test.c	buf[8] = 0;
	MOVLW	0x08
	ADDWF	r0x00, F
	MOVLW	0x00
	ADDWFC	r0x01, F
	MOVLW	0x00
	ADDWFC	r0x02, F
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVFF	r0x00, FSR0L
	MOVFF	r0x01, PRODL
	MOVF	r0x02, W
	CALL	__gptrput1
	MOVFF	PREINC1, r0x08
	MOVFF	PREINC1, r0x07
	MOVFF	PREINC1, r0x06
	MOVFF	PREINC1, r0x05
	MOVFF	PREINC1, r0x04
	MOVFF	PREINC1, r0x03
	MOVFF	PREINC1, r0x02
	MOVFF	PREINC1, r0x01
	MOVFF	PREINC1, r0x00
	MOVFF	PREINC1, FSR2L
	RETURN	

; ; Starting pCode block
S_ir_test__debug	code
_debug:
	.line	390; ir_test.c	void debug(unsigned char *s) {
	MOVFF	FSR2L, POSTDEC1
	MOVFF	FSR1L, FSR2L
	MOVFF	r0x00, POSTDEC1
	MOVFF	r0x01, POSTDEC1
	MOVFF	r0x02, POSTDEC1
	MOVFF	r0x03, POSTDEC1
	MOVFF	r0x04, POSTDEC1
	MOVFF	r0x05, POSTDEC1
	MOVFF	r0x06, POSTDEC1
	MOVLW	0x02
	MOVFF	PLUSW2, r0x00
	MOVLW	0x03
	MOVFF	PLUSW2, r0x01
	MOVLW	0x04
	MOVFF	PLUSW2, r0x02
	.line	393; ir_test.c	lcd_clear();
	CALL	_lcd_clear
	.line	394; ir_test.c	for (i = 0; i < 8; i++) {
	CLRF	r0x03
_00254_DS_:
	MOVLW	0x08
	SUBWF	r0x03, W
	BC	_00257_DS_
	.line	395; ir_test.c	if (!s[i]) {
	MOVF	r0x03, W
	ADDWF	r0x00, W
	MOVWF	r0x04
	CLRF	WREG
	ADDWFC	r0x01, W
	MOVWF	r0x05
	CLRF	WREG
	ADDWFC	r0x02, W
	MOVWF	r0x06
	MOVFF	r0x04, FSR0L
	MOVFF	r0x05, PRODL
	MOVF	r0x06, W
	CALL	__gptrget1
	MOVWF	r0x04
	MOVF	r0x04, W
	.line	396; ir_test.c	return;
	BZ	_00262_DS_
	.line	398; ir_test.c	send_data(s[i]);
	MOVF	r0x04, W
	MOVWF	POSTDEC1
	CALL	_send_data
	INCF	FSR1L, F
	.line	394; ir_test.c	for (i = 0; i < 8; i++) {
	INCF	r0x03, F
	BRA	_00254_DS_
_00257_DS_:
	.line	401; ir_test.c	lcd_ddram(SECOND_LINE);
	MOVLW	0x40
	MOVWF	POSTDEC1
	CALL	_lcd_ddram
	INCF	FSR1L, F
	.line	403; ir_test.c	for (i = 0; i < 8; i++) {
	CLRF	r0x03
_00258_DS_:
	MOVLW	0x08
	SUBWF	r0x03, W
	BC	_00262_DS_
	.line	404; ir_test.c	if (!s[i + 8]) {
	MOVFF	r0x03, r0x04
	CLRF	r0x05
	MOVLW	0x08
	ADDWF	r0x04, F
	BTFSC	STATUS, 0
	INCF	r0x05, F
	CLRF	r0x06
	BTFSC	r0x05, 7
	SETF	r0x06
	MOVF	r0x00, W
	ADDWF	r0x04, F
	MOVF	r0x01, W
	ADDWFC	r0x05, F
	MOVF	r0x02, W
	ADDWFC	r0x06, F
	MOVFF	r0x04, FSR0L
	MOVFF	r0x05, PRODL
	MOVF	r0x06, W
	CALL	__gptrget1
	MOVWF	r0x04
	MOVF	r0x04, W
	.line	405; ir_test.c	return;
	BZ	_00262_DS_
	.line	407; ir_test.c	send_data(s[i + 8]);
	MOVF	r0x04, W
	MOVWF	POSTDEC1
	CALL	_send_data
	INCF	FSR1L, F
	.line	403; ir_test.c	for (i = 0; i < 8; i++) {
	INCF	r0x03, F
	BRA	_00258_DS_
_00262_DS_:
	MOVFF	PREINC1, r0x06
	MOVFF	PREINC1, r0x05
	MOVFF	PREINC1, r0x04
	MOVFF	PREINC1, r0x03
	MOVFF	PREINC1, r0x02
	MOVFF	PREINC1, r0x01
	MOVFF	PREINC1, r0x00
	MOVFF	PREINC1, FSR2L
	RETURN	

; ; Starting pCode block
S_ir_test__debug_led	code
_debug_led:
	.line	372; ir_test.c	void debug_led(unsigned char s) {
	MOVFF	FSR2L, POSTDEC1
	MOVFF	FSR1L, FSR2L
	MOVFF	r0x00, POSTDEC1
	MOVFF	r0x01, POSTDEC1
	MOVFF	r0x02, POSTDEC1
	MOVFF	r0x03, POSTDEC1
	MOVFF	r0x04, POSTDEC1
	MOVFF	r0x05, POSTDEC1
	MOVLW	0x02
	MOVFF	PLUSW2, r0x00
	.line	374; ir_test.c	for (i = 0; i < 8; i++) {
	CLRF	r0x01
_00230_DS_:
	MOVLW	0x08
	SUBWF	r0x01, W
	BTFSC	STATUS, 0
	BRA	_00234_DS_
	.line	375; ir_test.c	if ((s & (1 << i)) >> i) {
	MOVLW	0x01
	MOVWF	r0x02
	MOVLW	0x00
	MOVWF	r0x03
	MOVF	r0x01, W
	BZ	_00241_DS_
	NEGF	WREG
	BCF	STATUS, 0
_00242_DS_:
	RLCF	r0x02, F
	RLCF	r0x03, F
	ADDLW	0x01
	BNC	_00242_DS_
_00241_DS_:
	MOVFF	r0x00, r0x04
	CLRF	r0x05
	MOVF	r0x04, W
	ANDWF	r0x02, F
	MOVF	r0x05, W
	ANDWF	r0x03, F
	MOVF	r0x01, W
	BZ	_00244_DS_
	NEGF	WREG
	BCF	STATUS, 0
_00245_DS_:
	BTFSC	r0x03, 7
	BSF	STATUS, 0
	RRCF	r0x03, F
	RRCF	r0x02, F
	ADDLW	0x01
	BNC	_00245_DS_
_00244_DS_:
	MOVF	r0x02, W
	IORWF	r0x03, W
	BZ	_00228_DS_
	.line	376; ir_test.c	LED_PIN = 1;
	BSF	_PORTBbits, 5
	.line	377; ir_test.c	sleep_ms(560);
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x02
	MOVWF	POSTDEC1
	MOVLW	0x30
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	378; ir_test.c	LED_PIN = 0;
	BCF	_PORTBbits, 5
	.line	379; ir_test.c	sleep_ms(40);
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x28
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	BRA	_00232_DS_
_00228_DS_:
	.line	382; ir_test.c	LED_PIN = 1;
	BSF	_PORTBbits, 5
	.line	383; ir_test.c	sleep_ms(40);
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x28
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	384; ir_test.c	LED_PIN = 0;
	BCF	_PORTBbits, 5
	.line	385; ir_test.c	sleep_ms(560);
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x02
	MOVWF	POSTDEC1
	MOVLW	0x30
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
_00232_DS_:
	.line	374; ir_test.c	for (i = 0; i < 8; i++) {
	INCF	r0x01, F
	BRA	_00230_DS_
_00234_DS_:
	MOVFF	PREINC1, r0x05
	MOVFF	PREINC1, r0x04
	MOVFF	PREINC1, r0x03
	MOVFF	PREINC1, r0x02
	MOVFF	PREINC1, r0x01
	MOVFF	PREINC1, r0x00
	MOVFF	PREINC1, FSR2L
	RETURN	

; ; Starting pCode block
S_ir_test__timer_control	code
_timer_control:
	.line	341; ir_test.c	static void timer_control(void) __interrupt 2 {
	MOVFF	WREG, POSTDEC1
	MOVFF	STATUS, POSTDEC1
	MOVFF	BSR, POSTDEC1
	MOVFF	PRODL, POSTDEC1
	MOVFF	PRODH, POSTDEC1
	MOVFF	FSR0L, POSTDEC1
	MOVFF	FSR0H, POSTDEC1
	MOVFF	PCLATH, POSTDEC1
	MOVFF	PCLATU, POSTDEC1
	MOVFF	FSR2L, POSTDEC1
	MOVFF	FSR1L, FSR2L
	MOVFF	r0x00, POSTDEC1
	MOVFF	r0x01, POSTDEC1
	.line	342; ir_test.c	if (PIR1bits.TMR2IF) {
	BTFSS	_PIR1bits, 1
	BRA	_00213_DS_
	.line	343; ir_test.c	PR2 = TIMER2_RELOAD;		// 1 ms delay at 8 MHz
	MOVLW	0x7c
	MOVWF	_PR2
	.line	344; ir_test.c	PIR1bits.TMR2IF = 0;
	BCF	_PIR1bits, 1
	BANKSEL	_timer_2
	.line	345; ir_test.c	timer_2++;
	INCF	_timer_2, F, B
	BNC	_10276_DS_
	BANKSEL	(_timer_2 + 1)
	INCF	(_timer_2 + 1), F, B
_10276_DS_:
	BNC	_20277_DS_
	BANKSEL	(_timer_2 + 2)
	INCF	(_timer_2 + 2), F, B
_20277_DS_:
	BNC	_30278_DS_
	BANKSEL	(_timer_2 + 3)
	INCF	(_timer_2 + 3), F, B
_30278_DS_:
_00213_DS_:
	.line	347; ir_test.c	if (PIR2bits.TMR3IF) {
	BTFSS	_PIR2bits, 1
	BRA	_00222_DS_
	.line	348; ir_test.c	TMR3H = (unsigned char)(TIMER3_RELOAD >> 8);	// 8 ms delay at 8 MHz
	CLRF	_TMR3H
	.line	349; ir_test.c	TMR3L = (unsigned char)TIMER3_RELOAD;
	CLRF	_TMR3L
	.line	350; ir_test.c	PIR2bits.TMR3IF = 0;	/* Clear the Timer Flag  */
	BCF	_PIR2bits, 1
	.line	354; ir_test.c	adc_setchannel(0);
	MOVLW	0x00
	MOVWF	POSTDEC1
	CALL	_adc_setchannel
	INCF	FSR1L, F
	.line	355; ir_test.c	adc_conv();
	CALL	_adc_conv
_00214_DS_:
	.line	356; ir_test.c	while(adc_busy()) {
	CALL	_adc_busy
	MOVWF	r0x00
	MOVF	r0x00, W
	BNZ	_00214_DS_
	.line	359; ir_test.c	ad0 = 0xff - (adc_read() >> 2);		// potmetrene vender omvendt på boardet
	CALL	_adc_read
	MOVWF	r0x00
	MOVFF	PRODL, r0x01
	RLCF	r0x01, W
	RRCF	r0x01, F
	RRCF	r0x00, F
	RLCF	r0x01, W
	RRCF	r0x01, F
	RRCF	r0x00, F
	MOVF	r0x00, W
	SUBLW	0xff
	BANKSEL	_ad0
	MOVWF	_ad0, B
	.line	362; ir_test.c	adc_setchannel(1);
	MOVLW	0x01
	MOVWF	POSTDEC1
	CALL	_adc_setchannel
	INCF	FSR1L, F
	.line	363; ir_test.c	adc_conv();
	CALL	_adc_conv
_00217_DS_:
	.line	364; ir_test.c	while(adc_busy()) {
	CALL	_adc_busy
	MOVWF	r0x00
	MOVF	r0x00, W
	BNZ	_00217_DS_
	.line	367; ir_test.c	ad1 = 0xff - (adc_read() >> 2);		// potmetrene vender omvendt på boardet
	CALL	_adc_read
	MOVWF	r0x00
	MOVFF	PRODL, r0x01
	RLCF	r0x01, W
	RRCF	r0x01, F
	RRCF	r0x00, F
	RLCF	r0x01, W
	RRCF	r0x01, F
	RRCF	r0x00, F
	MOVF	r0x00, W
	SUBLW	0xff
	BANKSEL	_ad1
	MOVWF	_ad1, B
_00222_DS_:
	MOVFF	PREINC1, r0x01
	MOVFF	PREINC1, r0x00
	MOVFF	PREINC1, FSR2L
	MOVFF	PREINC1, PCLATU
	MOVFF	PREINC1, PCLATH
	MOVFF	PREINC1, FSR0H
	MOVFF	PREINC1, FSR0L
	MOVFF	PREINC1, PRODH
	MOVFF	PREINC1, PRODL
	MOVFF	PREINC1, BSR
	MOVFF	PREINC1, STATUS
	MOVFF	PREINC1, WREG
	RETFIE	

; ; Starting pCode block
S_ir_test__phase_control	code
_phase_control:
	.line	320; ir_test.c	static void phase_control(void) __interrupt 1 {
	MOVFF	WREG, POSTDEC1
	MOVFF	STATUS, POSTDEC1
	MOVFF	BSR, POSTDEC1
	MOVFF	PRODL, POSTDEC1
	MOVFF	PRODH, POSTDEC1
	MOVFF	FSR0L, POSTDEC1
	MOVFF	FSR0H, POSTDEC1
	MOVFF	PCLATH, POSTDEC1
	MOVFF	PCLATU, POSTDEC1
	MOVFF	FSR2L, POSTDEC1
	MOVFF	FSR1L, FSR2L
	MOVFF	r0x00, POSTDEC1
	MOVFF	r0x01, POSTDEC1
	.line	321; ir_test.c	if (INTCONbits.TMR0IF) {	// 416,6 us delay at 20 MHz
	BTFSS	_INTCONbits, 2
	BRA	_00200_DS_
	.line	322; ir_test.c	TMR0H = (unsigned char)(TIMER0_RELOAD >> 8);
	MOVLW	0xf7
	MOVWF	_TMR0H
	.line	323; ir_test.c	TMR0L = (unsigned char)TIMER0_RELOAD;	/* Reload the Timer ASAP */
	MOVLW	0xfd
	MOVWF	_TMR0L
	.line	324; ir_test.c	INTCONbits.TMR0IF = 0;	/* Clear the Timer Flag  */
	BCF	_INTCONbits, 2
	.line	326; ir_test.c	if (serial_packet & (1 << serial_packet_bit_counter)) {
	MOVLW	0x01
	MOVWF	r0x00
	MOVLW	0x00
	MOVWF	r0x01
	BANKSEL	_serial_packet_bit_counter
	MOVF	_serial_packet_bit_counter, W, B
	BZ	_00205_DS_
	NEGF	WREG
	BCF	STATUS, 0
_00206_DS_:
	RLCF	r0x00, F
	RLCF	r0x01, F
	ADDLW	0x01
	BNC	_00206_DS_
_00205_DS_:
	BANKSEL	_serial_packet
	MOVF	_serial_packet, W, B
	ANDWF	r0x00, F
	BANKSEL	(_serial_packet + 1)
	MOVF	(_serial_packet + 1), W, B
	ANDWF	r0x01, F
	MOVF	r0x00, W
	IORWF	r0x01, W
	BZ	_00194_DS_
	.line	327; ir_test.c	send_mark();
	CALL	_send_mark
	BRA	_00195_DS_
_00194_DS_:
	.line	330; ir_test.c	send_space();
	CALL	_send_space
_00195_DS_:
	BANKSEL	_serial_packet_bit_counter
	.line	332; ir_test.c	serial_packet_bit_counter++;
	INCF	_serial_packet_bit_counter, F, B
	.line	333; ir_test.c	if (serial_packet_bit_counter >= 11) {
	MOVLW	0x0b
	BANKSEL	_serial_packet_bit_counter
	SUBWF	_serial_packet_bit_counter, W, B
	BNC	_00200_DS_
	BANKSEL	_serial_packet_bit_counter
	.line	334; ir_test.c	serial_packet_bit_counter = 0;
	CLRF	_serial_packet_bit_counter, B
	.line	335; ir_test.c	T0CONbits.TMR0ON = 0;
	BCF	_T0CONbits, 7
	.line	336; ir_test.c	INTCONbits.T0IE = 0;
	BCF	_INTCONbits, 5
_00200_DS_:
	MOVFF	PREINC1, r0x01
	MOVFF	PREINC1, r0x00
	MOVFF	PREINC1, FSR2L
	MOVFF	PREINC1, PCLATU
	MOVFF	PREINC1, PCLATH
	MOVFF	PREINC1, FSR0H
	MOVFF	PREINC1, FSR0L
	MOVFF	PREINC1, PRODH
	MOVFF	PREINC1, PRODL
	MOVFF	PREINC1, BSR
	MOVFF	PREINC1, STATUS
	MOVFF	PREINC1, WREG
	RETFIE	

; ; Starting pCode block
S_ir_test__sleep_ms	code
_sleep_ms:
	.line	310; ir_test.c	void sleep_ms(unsigned long ms) {
	MOVFF	FSR2L, POSTDEC1
	MOVFF	FSR1L, FSR2L
	MOVFF	r0x00, POSTDEC1
	MOVFF	r0x01, POSTDEC1
	MOVFF	r0x02, POSTDEC1
	MOVFF	r0x03, POSTDEC1
	MOVFF	r0x04, POSTDEC1
	MOVFF	r0x05, POSTDEC1
	MOVFF	r0x06, POSTDEC1
	MOVFF	r0x07, POSTDEC1
	MOVFF	r0x08, POSTDEC1
	MOVFF	r0x09, POSTDEC1
	MOVFF	r0x0a, POSTDEC1
	MOVFF	r0x0b, POSTDEC1
	MOVFF	r0x0c, POSTDEC1
	MOVFF	r0x0d, POSTDEC1
	MOVFF	r0x0e, POSTDEC1
	MOVFF	r0x0f, POSTDEC1
	MOVLW	0x02
	MOVFF	PLUSW2, r0x00
	MOVLW	0x03
	MOVFF	PLUSW2, r0x01
	MOVLW	0x04
	MOVFF	PLUSW2, r0x02
	MOVLW	0x05
	MOVFF	PLUSW2, r0x03
	.line	313; ir_test.c	start_timer_2 = timer_2;
	MOVFF	_timer_2, r0x04
	MOVFF	(_timer_2 + 1), r0x05
	MOVFF	(_timer_2 + 2), r0x06
	MOVFF	(_timer_2 + 3), r0x07
_00179_DS_:
	.line	315; ir_test.c	while ( (((signed long)(timer_2 - start_timer_2) < 0) ? (-1 * (timer_2 - start_timer_2)) : (timer_2 - start_timer_2)) < ms) {
	MOVF	r0x04, W
	BANKSEL	_timer_2
	SUBWF	_timer_2, W, B
	MOVWF	r0x08
	MOVF	r0x05, W
	BANKSEL	(_timer_2 + 1)
	SUBWFB	(_timer_2 + 1), W, B
	MOVWF	r0x09
	MOVF	r0x06, W
	BANKSEL	(_timer_2 + 2)
	SUBWFB	(_timer_2 + 2), W, B
	MOVWF	r0x0a
	MOVF	r0x07, W
	BANKSEL	(_timer_2 + 3)
	SUBWFB	(_timer_2 + 3), W, B
	MOVWF	r0x0b
	MOVFF	r0x08, r0x0c
	MOVFF	r0x09, r0x0d
	MOVFF	r0x0a, r0x0e
	MOVFF	r0x0b, r0x0f
	BSF	STATUS, 0
	BTFSS	r0x0f, 7
	BCF	STATUS, 0
	BNC	_00184_DS_
	MOVF	r0x0b, W
	MOVWF	POSTDEC1
	MOVF	r0x0a, W
	MOVWF	POSTDEC1
	MOVF	r0x09, W
	MOVWF	POSTDEC1
	MOVF	r0x08, W
	MOVWF	POSTDEC1
	MOVLW	0xff
	MOVWF	POSTDEC1
	MOVLW	0xff
	MOVWF	POSTDEC1
	MOVLW	0xff
	MOVWF	POSTDEC1
	MOVLW	0xff
	MOVWF	POSTDEC1
	CALL	__mullong
	MOVWF	r0x0c
	MOVFF	PRODL, r0x0d
	MOVFF	PRODH, r0x0e
	MOVFF	FSR0L, r0x0f
	MOVLW	0x08
	ADDWF	FSR1L, F
	BRA	_00185_DS_
_00184_DS_:
	MOVFF	r0x08, r0x0c
	MOVFF	r0x09, r0x0d
	MOVFF	r0x0a, r0x0e
	MOVFF	r0x0b, r0x0f
_00185_DS_:
	MOVF	r0x03, W
	SUBWF	r0x0f, W
	BNZ	_00188_DS_
	MOVF	r0x02, W
	SUBWF	r0x0e, W
	BNZ	_00188_DS_
	MOVF	r0x01, W
	SUBWF	r0x0d, W
	BNZ	_00188_DS_
	MOVF	r0x00, W
	SUBWF	r0x0c, W
_00188_DS_:
	BTFSS	STATUS, 0
	BRA	_00179_DS_
	MOVFF	PREINC1, r0x0f
	MOVFF	PREINC1, r0x0e
	MOVFF	PREINC1, r0x0d
	MOVFF	PREINC1, r0x0c
	MOVFF	PREINC1, r0x0b
	MOVFF	PREINC1, r0x0a
	MOVFF	PREINC1, r0x09
	MOVFF	PREINC1, r0x08
	MOVFF	PREINC1, r0x07
	MOVFF	PREINC1, r0x06
	MOVFF	PREINC1, r0x05
	MOVFF	PREINC1, r0x04
	MOVFF	PREINC1, r0x03
	MOVFF	PREINC1, r0x02
	MOVFF	PREINC1, r0x01
	MOVFF	PREINC1, r0x00
	MOVFF	PREINC1, FSR2L
	RETURN	

; ; Starting pCode block
S_ir_test__send_mark	code
_send_mark:
	.line	258; ir_test.c	void send_mark() {
	MOVFF	FSR2L, POSTDEC1
	MOVFF	FSR1L, FSR2L
	MOVFF	r0x00, POSTDEC1
	BANKSEL	_tx_bit_counter
	.line	260; ir_test.c	for (tx_bit_counter = 0; tx_bit_counter < 30; tx_bit_counter++) {
	CLRF	_tx_bit_counter, B
_00166_DS_:
	MOVLW	0x1e
	BANKSEL	_tx_bit_counter
	SUBWF	_tx_bit_counter, W, B
	BTFSC	STATUS, 0
	BRA	_00170_DS_
	.line	261; ir_test.c	TX_PIN ^= 1;
	CLRF	r0x00
	BTFSC	_PORTCbits, 6
	INCF	r0x00, F
	MOVLW	0x01
	XORWF	r0x00, F
	MOVF	r0x00, W
	ANDLW	0x01
	RRNCF	WREG, W
	RRNCF	WREG, W
	MOVWF	PRODH
	MOVF	_PORTCbits, W
	ANDLW	0xbf
	IORWF	PRODH, W
	MOVWF	_PORTCbits
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	
	BANKSEL	_tx_bit_counter
	.line	260; ir_test.c	for (tx_bit_counter = 0; tx_bit_counter < 30; tx_bit_counter++) {
	INCF	_tx_bit_counter, F, B
	BRA	_00166_DS_
_00170_DS_:
	MOVFF	PREINC1, r0x00
	MOVFF	PREINC1, FSR2L
	RETURN	

; ; Starting pCode block
S_ir_test__send_space	code
_send_space:
	.line	253; ir_test.c	void send_space() {
	MOVFF	FSR2L, POSTDEC1
	MOVFF	FSR1L, FSR2L
	.line	255; ir_test.c	TX_PIN = 0;
	BCF	_PORTCbits, 6
	MOVFF	PREINC1, FSR2L
	RETURN	

; ; Starting pCode block
S_ir_test__rs232_receive	code
_rs232_receive:
	.line	228; ir_test.c	unsigned char rs232_receive(unsigned char *s, unsigned long timeout) {
	MOVFF	FSR2L, POSTDEC1
	MOVFF	FSR1L, FSR2L
	MOVFF	r0x00, POSTDEC1
	MOVFF	r0x01, POSTDEC1
	MOVFF	r0x02, POSTDEC1
	MOVFF	r0x03, POSTDEC1
	MOVFF	r0x04, POSTDEC1
	MOVFF	r0x05, POSTDEC1
	MOVFF	r0x06, POSTDEC1
	MOVFF	r0x07, POSTDEC1
	MOVFF	r0x08, POSTDEC1
	MOVFF	r0x09, POSTDEC1
	MOVFF	r0x0a, POSTDEC1
	MOVFF	r0x0b, POSTDEC1
	MOVFF	r0x0c, POSTDEC1
	MOVFF	r0x0d, POSTDEC1
	MOVFF	r0x0e, POSTDEC1
	MOVFF	r0x0f, POSTDEC1
	MOVFF	r0x10, POSTDEC1
	MOVFF	r0x11, POSTDEC1
	MOVFF	r0x12, POSTDEC1
	MOVLW	0x02
	MOVFF	PLUSW2, r0x00
	MOVLW	0x03
	MOVFF	PLUSW2, r0x01
	MOVLW	0x04
	MOVFF	PLUSW2, r0x02
	MOVLW	0x05
	MOVFF	PLUSW2, r0x03
	MOVLW	0x06
	MOVFF	PLUSW2, r0x04
	MOVLW	0x07
	MOVFF	PLUSW2, r0x05
	MOVLW	0x08
	MOVFF	PLUSW2, r0x06
	.line	235; ir_test.c	133	// 9600 kbps
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x85
	MOVWF	POSTDEC1
	MOVLW	0x2c
	CALL	_usart_open
	MOVLW	0x02
	ADDWF	FSR1L, F
	.line	237; ir_test.c	TXSTAbits.TXEN = 0;	// use software usart for sending data
	BCF	_TXSTAbits, 5
	.line	238; ir_test.c	BAUDCONbits.RXDTP = 1;
	BSF	_BAUDCONbits, 5
	.line	240; ir_test.c	start_timer_2 = timer_2;
	MOVFF	_timer_2, r0x07
	MOVFF	(_timer_2 + 1), r0x08
	MOVFF	(_timer_2 + 2), r0x09
	MOVFF	(_timer_2 + 3), r0x0a
_00145_DS_:
	.line	241; ir_test.c	while(!usart_drdy()) {
	CALL	_usart_drdy
	MOVWF	r0x0b
	MOVF	r0x0b, W
	BTFSS	STATUS, 2
	BRA	_00147_DS_
	.line	243; ir_test.c	if ( (((signed long)(timer_2 - start_timer_2) < 0) ? (-1 * (timer_2 - start_timer_2)) : (timer_2 - start_timer_2)) > timeout) {
	MOVF	r0x07, W
	BANKSEL	_timer_2
	SUBWF	_timer_2, W, B
	MOVWF	r0x0b
	MOVF	r0x08, W
	BANKSEL	(_timer_2 + 1)
	SUBWFB	(_timer_2 + 1), W, B
	MOVWF	r0x0c
	MOVF	r0x09, W
	BANKSEL	(_timer_2 + 2)
	SUBWFB	(_timer_2 + 2), W, B
	MOVWF	r0x0d
	MOVF	r0x0a, W
	BANKSEL	(_timer_2 + 3)
	SUBWFB	(_timer_2 + 3), W, B
	MOVWF	r0x0e
	MOVFF	r0x0b, r0x0f
	MOVFF	r0x0c, r0x10
	MOVFF	r0x0d, r0x11
	MOVFF	r0x0e, r0x12
	BSF	STATUS, 0
	BTFSS	r0x12, 7
	BCF	STATUS, 0
	BNC	_00150_DS_
	MOVF	r0x0e, W
	MOVWF	POSTDEC1
	MOVF	r0x0d, W
	MOVWF	POSTDEC1
	MOVF	r0x0c, W
	MOVWF	POSTDEC1
	MOVF	r0x0b, W
	MOVWF	POSTDEC1
	MOVLW	0xff
	MOVWF	POSTDEC1
	MOVLW	0xff
	MOVWF	POSTDEC1
	MOVLW	0xff
	MOVWF	POSTDEC1
	MOVLW	0xff
	MOVWF	POSTDEC1
	CALL	__mullong
	MOVWF	r0x0f
	MOVFF	PRODL, r0x10
	MOVFF	PRODH, r0x11
	MOVFF	FSR0L, r0x12
	MOVLW	0x08
	ADDWF	FSR1L, F
	BRA	_00151_DS_
_00150_DS_:
	MOVFF	r0x0b, r0x0f
	MOVFF	r0x0c, r0x10
	MOVFF	r0x0d, r0x11
	MOVFF	r0x0e, r0x12
_00151_DS_:
	MOVF	r0x12, W
	SUBWF	r0x06, W
	BNZ	_00156_DS_
	MOVF	r0x11, W
	SUBWF	r0x05, W
	BNZ	_00156_DS_
	MOVF	r0x10, W
	SUBWF	r0x04, W
	BNZ	_00156_DS_
	MOVF	r0x0f, W
	SUBWF	r0x03, W
_00156_DS_:
	BTFSC	STATUS, 0
	BRA	_00145_DS_
	.line	244; ir_test.c	usart_close();
	CALL	_usart_close
	.line	245; ir_test.c	return 0;
	CLRF	WREG
	BRA	_00148_DS_
_00147_DS_:
	.line	248; ir_test.c	*s = usart_getc();
	CALL	_usart_getc
	MOVWF	r0x03
	MOVFF	r0x03, POSTDEC1
	MOVFF	r0x00, FSR0L
	MOVFF	r0x01, PRODL
	MOVF	r0x02, W
	CALL	__gptrput1
	.line	249; ir_test.c	usart_close();
	CALL	_usart_close
	.line	250; ir_test.c	return 1;
	MOVLW	0x01
_00148_DS_:
	MOVFF	PREINC1, r0x12
	MOVFF	PREINC1, r0x11
	MOVFF	PREINC1, r0x10
	MOVFF	PREINC1, r0x0f
	MOVFF	PREINC1, r0x0e
	MOVFF	PREINC1, r0x0d
	MOVFF	PREINC1, r0x0c
	MOVFF	PREINC1, r0x0b
	MOVFF	PREINC1, r0x0a
	MOVFF	PREINC1, r0x09
	MOVFF	PREINC1, r0x08
	MOVFF	PREINC1, r0x07
	MOVFF	PREINC1, r0x06
	MOVFF	PREINC1, r0x05
	MOVFF	PREINC1, r0x04
	MOVFF	PREINC1, r0x03
	MOVFF	PREINC1, r0x02
	MOVFF	PREINC1, r0x01
	MOVFF	PREINC1, r0x00
	MOVFF	PREINC1, FSR2L
	RETURN	

; ; Starting pCode block
S_ir_test__rs232_transmit	code
_rs232_transmit:
	.line	216; ir_test.c	void rs232_transmit(unsigned char s) {
	MOVFF	FSR2L, POSTDEC1
	MOVFF	FSR1L, FSR2L
	MOVFF	r0x00, POSTDEC1
	MOVFF	r0x01, POSTDEC1
	MOVFF	r0x02, POSTDEC1
	MOVFF	r0x03, POSTDEC1
	MOVLW	0x02
	MOVFF	PLUSW2, r0x00
	.line	218; ir_test.c	serial_packet = 1 | (s << 2) | (1 << 10);
	CLRF	r0x01
	MOVF	r0x00, W
	MOVWF	r0x02
	ADDWF	r0x02, F
	RLCF	r0x01, W
	MOVWF	r0x03
	BCF	STATUS, 0
	RLCF	r0x02, F
	RLCF	r0x03, F
	MOVLW	0x01
	IORWF	r0x02, W
	BANKSEL	_serial_packet
	MOVWF	_serial_packet, B
	MOVLW	0x04
	IORWF	r0x03, W
	BANKSEL	(_serial_packet + 1)
	MOVWF	(_serial_packet + 1), B
	BANKSEL	_serial_packet_bit_counter
	.line	219; ir_test.c	serial_packet_bit_counter = 0;
	CLRF	_serial_packet_bit_counter, B
	.line	222; ir_test.c	INTCONbits.TMR0IF = 1;	/* Force Instant entry to Timer 0 Interrupt */
	BSF	_INTCONbits, 2
	.line	223; ir_test.c	T0CONbits.TMR0ON = 1;	// enable timer0
	BSF	_T0CONbits, 7
	.line	224; ir_test.c	INTCONbits.T0IE = 1;	/* Ensure that TMR0 Interrupt is enabled    */
	BSF	_INTCONbits, 5
	.line	225; ir_test.c	sleep_ms(5);			// wait for tx
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x05
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	MOVFF	PREINC1, r0x03
	MOVFF	PREINC1, r0x02
	MOVFF	PREINC1, r0x01
	MOVFF	PREINC1, r0x00
	MOVFF	PREINC1, FSR2L
	RETURN	

; ; Starting pCode block
__str_0:
	DB	0x25, 0x30, 0x32, 0x78, 0x25, 0x30, 0x32, 0x78, 0x25, 0x30, 0x32, 0x78
	DB	0x25, 0x30, 0x32, 0x78, 0x25, 0x30, 0x32, 0x78, 0x25, 0x30, 0x32, 0x78
	DB	0x25, 0x30, 0x32, 0x78, 0x25, 0x30, 0x32, 0x78, 0x00


; Statistics:
; code size:	 3150 (0x0c4e) bytes ( 2.40%)
;           	 1575 (0x0627) words
; udata size:	  131 (0x0083) bytes ( 7.31%)
; access size:	   19 (0x0013) bytes


	end
